1. Field of the Invention
This invention relates generally to digital receiver systems. More particularly, the invention relates to a bit synchronizer for a digital receiver system that synchronizes to the transmitter clock in terms of bit timing in order to extract correct bit information for select receiver processes.
2. Discussion of the Related Art
It is well known that communication systems are a critical part of both commercial and military applications. In fact, as semiconductor technologies advance, the demand for digital communication systems continues to grow. Digital communication systems can be conceptually divided into systems that transmit and systems that receive. In order to meet requirements for faster, more reliable communications associated with the aforementioned demand for digital communication systems, a number of modulation/demodulation schemes have evolved. Two common modulation schemes used in digital systems are amplitude shift keying (ASK) and continuous phase frequency shift keying (CPFSK). The invention is intended to be applied to demodulated baseband signals (with modulation removed).
It is important to note that some digital receiver systems provide no mechanism for subsequent signal processing to alter the timing of the receiver""s sampling clock. This is when a baseband bit synchronizer comes into play. Bit synchronization is often obscured by received noise, signal fading, relative time drift, and time jitter between the received symbol sequence and the receiver sampling clock. Depending on the application, losses in bit synchronization can result in losses in critical data. It is therefore desirable to provide a bit synchronizer for a digital receiver system that is able to synchronize to the transmitter clock and extract the correct transmitted bit information.
The above and other objectives are achieved by a bit synchronization methodology for a digital receiver system in accordance with the present invention. The bit synchronizer has a DC level estimator for converting a sampled digital signal into a level-adjusted signal. A delay module generates a first timing signal, a second timing signal, and a third timing signal based on the level-adjusted signal. The first timing signal corresponds to the sum of the level-adjusted samples over a first bit or symbol interval, while the second timing signal corresponds to the sum of the level-adjusted samples over a second bit interval. Similarly, the third timing signal corresponds to the sum of the level-adjusted samples over a third bit interval. The bit synchronizer further includes a control module for generating an output signal based on the timing signals such that the polarity of the selected timing signal is used to determine the output bit value.
Further in accordance with the present invention, a control module for a bit synchronizer is provided. The control module has an absolute value stage for generating signals that are absolute values of the corresponding timing signals. An integration stage generates integrated signals, where the integrated signals represent the average energy of the corresponding timing signals over a predetermined integration length. The control module further includes a signal selector for generating an output signal by comparing the three integrated signals. The polarity of the timing signal corresponding to the largest integrated signal is used to determine the output bit value. The result is a more efficient digital receiver system that uses relative comparison instead of absolute thresholds for data selection. To maintain correct bit timing, the control module further adjusts the three timing windows by advancing or restarting the windows one sample at a time after each bit decision. The control module therefore eliminates excessive memory buffers, control logic, and time delays.
In another aspect of the invention a method for synchronizing the transmit and receive bit timing is provided. The method includes the step of converting the sampled digital signal into a level-adjusted signal. The method further includes the steps of generating a first timing signal, a second timing signal, and a third timing signal based on the level-adjusted signal. The method further provides for generating an output signal based on the timing signals such that the transmit and receive bit timing are synchronized.